1. Field of the Invention
The present invention relates to a solid state imaging device in which a plurality of pixels having a photoelectric conversion element, which converts input light into signal charges and accumulates the converted signal charges, are arranged.
Priority is claimed on Japanese Patent Application No. 2008-312726, filed Dec. 8, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
In the related art, a Metal Oxide Semiconductor (MOS) type solid state imaging device, which uses pixels having an amplification and reading function, is known. FIG. 5 shows the structure of a pixel of a MOS type solid state imaging device. As shown in FIG. 5, a single pixel 100a includes a photodiode 101, a transmission transistor 102, a charge retention (or Floating Diffusion (FD)) section 103, an FD reset transistor 104, an amplification transistor 105, and a selection transistor 106.
The photodiode 101 is photoelectric conversion element that converts input light into a signal charge and accumulates the converted signal charge.
The transmission transistor 102 sends the signal charge, accumulated in the photodiode 101, to the FD section 103. The FD section 103 maintains the signal charge, which is sent from the photodiode 101 by the transmission transistor 102. The FD reset transistor 104 resets the signal charge in the photodiode 101 and the FD section 103. The amplification transistor 105 amplifies the level of a voltage of the FD section 103 and outputs the amplified voltage as a pixel signal. The selection transistor 106 outputs the pixel signal to a vertical signal line 114 when the pixel 100a is selected as a pixel that reads out a signal charge. Herein, other components except for the photodiode 101 are shaded from light.
Inside the pixel 100a, a pixel power line 110, an FD reset line 111, a transmission line 112, and a selection line 113, as well as the vertical signal line 114, are arranged. The pixel power line 110 is a signal line for applying a supply voltage VDD, and is electrically connected to a drain side of the amplification transistor 105 and to a drain side of the FD reset transistor 104. The FD reset line 111 is a signal line for applying FD reset pulses φRMi (i=1 to m), which are for resetting FD sections 103 of one row, and is connected to gates of FD reset transistors 104 of one row.
The transmission line 112 is a signal line for applying row transmission pulses φTRi (i=1 to m), which are for sending signal charges of pixels of one row to the FD section 103 of each pixel, and is electrically connected to gates of transmission transistors 102 of the pixels of one row. The selection line 113 is a signal line for applying row selection pulses φSEi (i=1 to m), which are for selecting pixels of one row that read out pixel signals, and is electrically connected to gates of selection transistors 106 of the pixels of one row. Due to the structure of the pixel using the four transistors, a photoelectric conversion function, a reset function, an amplification and reading function, a temporary memory function, and a selection function are realized.
The MOS type solid state imaging device has a pixel array in which pixels having the above-described structure are arrayed in a matrix consisting of m rows×n columns. The MOS type solid state imaging device uses a typical XY address reading method, which reads pixel signals from all of the pixels by reading pixel signals in a per row by sequentially selecting each row from first row to mth row using a vertical scanning circuit and a horizontal scanning circuit (not shown).
In the typical XY address reading method, timings for sending signal charges to the FD sections 103 are different for each row. In more detail, in the first row in which the signal charges are initially read out and in the mth row in which the signal charges are read out for the last time, the greatest difference in the timings for reading the respective rows is as much as one frame. This causes a problem in that the image of a moving object is distorted if taken at high speed.
As an approach to solve the foregoing problem in the typical XY address reading method, there is a global shutter reading method. The global shutter reading method will be described hereinafter with reference to FIG. 6. First, photodiodes 101 of pixels of all of the rows are reset by simultaneously outputting FD reset pulses φRM1 to φRMm and row transmission pulses φTR1 to φTRm of all of the rows from a vertical scanning circuit (not shown). Subsequently, after a signal accumulation period (i.e., an exposure period) is passed, the row transmission pulses φTR1 to φTRm of all of the rows are simultaneously output from the vertical scanning circuit, and signal charges of the photodiodes 101 of the pixels of all of the rows, accumulated in the exposure period, are simultaneously sent to the FD sections 103. The operation of a global shutter is performed in the above described processing.
In addition, in the pixel structure as shown in FIG. 5, when strong light is incident on the photodiode 101, a signal charge equal to or more than the maximum amount of charge, which can be charged in the photodiode 101, is generated. This causes the problem of the so-called “blooming,” in which the signal charge flows out from the photodiode 101 and spills into the FD section 103, adjacent pixels, or the like through the transmission transistor 102 or a channel stop area. The “blooming” also occurs in the case of performing a global shutter operation by once sending the signal charges obtained by the photodiodes 101 to the FD sections 103, simultaneously across all of the pixels.
When the “blooming” occurs, a white stripe shape or a white circular pattern is observed in a photographing image, thereby degrading image quality. In the case of performing the global shutter operation, after the signal charge is sent to the FD section 103, an excessive charge occurred in the photodiode 101 also overflows into the FD section 103 in the pixel thereof. The excessive charge is then added to the signal charge sent to the FD section 103, thereby destroying the signal. This, as a result, increases the influence of the blooming.
As a method for suppressing the blooming from occurring in the case of performing the global shutter operation, there are the following methods. Specifically, Japanese Unexamined Patent Application Publication No. 2004-111590 and Japanese Unexamined Patent Application Publication No. 2005-42714 disclose a circuit structure shown in FIG. 7. With respect to the pixel 100a shown in FIG. 5, a Photodiode (PD) reset transistor 107, which directly resets the photodiode 101, is added to a pixel 100b, as shown in FIG. 7. In addition, a PD reset line 115, which applies a PD reset pulse φRPDi (i=1 to m) for resetting photodiodes 101 of one row, is added. The PD reset line 115 is connected to gates of PD reset transistors 107 of one row. In the disclosure of Japanese Unexamined Patent Application Publication No. 2004-111590 and Japanese Unexamined Patent Application Publication No. 2005-42714, a charge occurred in the photodiode 101 is output to the pixel power line 110 by turning on the PD reset transistor 107 using such a circuit structure, except for the exposure period.
Below, the operation of this method is explained with reference to FIG. 8. First, PD reset pulses φRPD1 to φRPDm of all of the rows, output from the vertical scanning circuit (not shown), are simultaneously converted from “H” level to “L” level, and the reset of the photodiodes 101 of the pixels of all of the rows is canceled, so that accumulation begins. Subsequently, after a certain signal accumulation period (i.e., an exposure period) is passed, row transmission pulses φTR1 to φTRm of all of the rows are simultaneously output from the vertical scanning circuit, so that the signal charges, accumulated in the photodiodes 101 of the pixels of all of the rows in the exposure period, are simultaneously sent to the FD sections 103.
Afterwards, selection pulses φSEi are sequentially input row by row, and pixel signals are read out row by row using a horizontal reading circuit (not shown). Before these pixel signals are read out, the PD reset pulses φRPD1 to φRPDm of all of the rows are simultaneously converted from “L” level to “H” level. Accordingly, the photodiodes 101 of the pixels of all of the rows are reset, and the charges occurred in the photodiodes 101 are discharged to the pixel power lines 110.